%0 Conference Paper
%A Brank, Bine
%A Pleiter, Dirk
%T Assessing the State of Autovectorization Support based on SVE
%I IEEE
%M FZJ-2022-04463
%P 556–562
%D 2022
%X So-called SIMD instructions, which trigger operations that process in each clock cycle a data tuple, have become widespread in modern processor architectures. In particular, processors for high-performance computing (HPC) systems rely on this additional level of parallelism to reach a high throughput of arithmetic operations. Leveraging these SIMD instructions can still be challenging for application software developers. This challenge has become simpler due to a compiler technique called auto-vectorization. In this paper, we explore the current state of auto-vectorization capabilities using state-of-the-art compilers using a recent extension of the Arm instruction set architecture, called SVE. We measure the performance gains on a recent processor architecture supporting SVE, namely the Fujitsu A64FX processor.
%B 2022 IEEE International Conference on Cluster Computing (CLUSTER)
%C 5 Sep 2022 - 8 Sep 2022, Heidelberg (Germany)
Y2 5 Sep 2022 - 8 Sep 2022
M2 Heidelberg, Germany
%F PUB:(DE-HGF)8
%9 Contribution to a conference proceedings
%U <Go to ISI:>//WOS:000920273100058
%R 10.1109/CLUSTER51413.2022.00073
%U https://juser.fz-juelich.de/record/911147