Contribution to a conference proceedings

FZJ-2022-04463

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Assessing the State of Autovectorization Support based on SVE

Brank, B. (Corresponding author)FZJ* ; Pleiter, D.

2022
IEEE

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Please use a persistent id in citations: http://hdl.handle.net/2128/32799  doi:10.1109/CLUSTER51413.2022.00073

Abstract: So-called SIMD instructions, which trigger operations that process in each clock cycle a data tuple, have become widespread in modern processor architectures. In particular, processors for high-performance computing (HPC) systems rely on this additional level of parallelism to reach a high throughput of arithmetic operations. Leveraging these SIMD instructions can still be challenging for application software developers. This challenge has become simpler due to a compiler technique called auto-vectorization. In this paper, we explore the current state of auto-vectorization capabilities using state-of-the-art compilers using a recent extension of the Arm instruction set architecture, called SVE. We measure the performance gains on a recent processor architecture supporting SVE, namely the Fujitsu A64FX processor.

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Contributing Institute(s):

1. Jülich Supercomputing Center (JSC)

Research Program(s):

1. 5122 - Future Computing & Big Data Systems (POF4-512) (POF4-512)
2. Mont-Blanc 2020 - Mont-Blanc 2020, European scalable, modular and power efficient HPC processor (779877) (779877)

Appears in the scientific report 2022

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