000911147 001__ 911147
000911147 005__ 20230224084249.0
000911147 0247_ $$2doi$$a10.1109/CLUSTER51413.2022.00073
000911147 0247_ $$2Handle$$a2128/32799
000911147 0247_ $$2WOS$$aWOS:000920273100058
000911147 037__ $$aFZJ-2022-04463
000911147 1001_ $$0P:(DE-Juel1)174207$$aBrank, Bine$$b0$$eCorresponding author
000911147 1112_ $$a2022 IEEE International Conference on Cluster Computing (CLUSTER)$$cHeidelberg$$d2022-09-05 - 2022-09-08$$wGermany
000911147 245__ $$aAssessing the State of Autovectorization Support based on SVE
000911147 260__ $$bIEEE$$c2022
000911147 300__ $$a556–562
000911147 3367_ $$2ORCID$$aCONFERENCE_PAPER
000911147 3367_ $$033$$2EndNote$$aConference Paper
000911147 3367_ $$2BibTeX$$aINPROCEEDINGS
000911147 3367_ $$2DRIVER$$aconferenceObject
000911147 3367_ $$2DataCite$$aOutput Types/Conference Paper
000911147 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib$$s1669378185_20905
000911147 520__ $$aSo-called SIMD instructions, which trigger operations that process in each clock cycle a data tuple, have become widespread in modern processor architectures. In particular, processors for high-performance computing (HPC) systems rely on this additional level of parallelism to reach a high throughput of arithmetic operations. Leveraging these SIMD instructions can still be challenging for application software developers. This challenge has become simpler due to a compiler technique called auto-vectorization. In this paper, we explore the current state of auto-vectorization capabilities using state-of-the-art compilers using a recent extension of the Arm instruction set architecture, called SVE. We measure the performance gains on a recent processor architecture supporting SVE, namely the Fujitsu A64FX processor.
000911147 536__ $$0G:(DE-HGF)POF4-5122$$a5122 - Future Computing & Big Data Systems (POF4-512)$$cPOF4-512$$fPOF IV$$x0
000911147 536__ $$0G:(EU-Grant)779877$$aMont-Blanc 2020 - Mont-Blanc 2020, European scalable, modular and power efficient HPC processor (779877)$$c779877$$fH2020-ICT-2017-1$$x1
000911147 588__ $$aDataset connected to CrossRef Conference
000911147 7001_ $$0P:(DE-HGF)0$$aPleiter, Dirk$$b1
000911147 773__ $$a10.1109/CLUSTER51413.2022.00073
000911147 8564_ $$uhttps://juser.fz-juelich.de/record/911147/files/EAHPC_2022_SVE_Vectorisation.pdf$$yOpenAccess
000911147 909CO $$ooai:juser.fz-juelich.de:911147$$pdnbdelivery$$pec_fundedresources$$pVDB$$pdriver$$popen_access$$popenaire
000911147 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)174207$$aForschungszentrum Jülich$$b0$$kFZJ
000911147 9131_ $$0G:(DE-HGF)POF4-512$$1G:(DE-HGF)POF4-510$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5122$$aDE-HGF$$bKey Technologies$$lEngineering Digital Futures – Supercomputing, Data Management and Information Security for Knowledge and Action$$vSupercomputing & Big Data Infrastructures$$x0
000911147 9141_ $$y2022
000911147 915__ $$0StatID:(DE-HGF)0510$$2StatID$$aOpenAccess
000911147 9201_ $$0I:(DE-Juel1)JSC-20090406$$kJSC$$lJülich Supercomputing Center$$x0
000911147 980__ $$acontrib
000911147 980__ $$aVDB
000911147 980__ $$aUNRESTRICTED
000911147 980__ $$aI:(DE-Juel1)JSC-20090406
000911147 9801_ $$aFullTexts