TY  - CONF
AU  - Brank, Bine
AU  - Pleiter, Dirk
TI  - Assessing the State of Autovectorization Support based on SVE
PB  - IEEE
M1  - FZJ-2022-04463
SP  - 556–562
PY  - 2022
AB  - So-called SIMD instructions, which trigger operations that process in each clock cycle a data tuple, have become widespread in modern processor architectures. In particular, processors for high-performance computing (HPC) systems rely on this additional level of parallelism to reach a high throughput of arithmetic operations. Leveraging these SIMD instructions can still be challenging for application software developers. This challenge has become simpler due to a compiler technique called auto-vectorization. In this paper, we explore the current state of auto-vectorization capabilities using state-of-the-art compilers using a recent extension of the Arm instruction set architecture, called SVE. We measure the performance gains on a recent processor architecture supporting SVE, namely the Fujitsu A64FX processor.
T2  - 2022 IEEE International Conference on Cluster Computing (CLUSTER)
CY  - 5 Sep 2022 - 8 Sep 2022, Heidelberg (Germany)
Y2  - 5 Sep 2022 - 8 Sep 2022
M2  - Heidelberg, Germany
LB  - PUB:(DE-HGF)8
UR  - <Go to ISI:>//WOS:000920273100058
DO  - DOI:10.1109/CLUSTER51413.2022.00073
UR  - https://juser.fz-juelich.de/record/911147
ER  -