Home > Publications database > Resilience in (Time-Parallel) Spectral Deferred Corrections |
Talk (non-conference) (Invited) | FZJ-2022-05254 |
2022
Please use a persistent id in citations: http://hdl.handle.net/2128/32842
Abstract: Advancement in computational speed is nowadays gained by using more processing units rather than faster ones. Faults in the processing units caused by numerous sources including radiation and aging have been neglected in the past. However, the increasing size of HPC machines makes them more susceptible and it is important to develop a resilience strategy to avoid losing millions of CPU hours. Parallel-in-time methods target the very largest of computers and are hence required to come with algorithm-based fault tolerance. We look here at spectral deferred corrections (SDC), which is a time marching scheme that is at the heart of parallel-in-time methods such as PFASST. Due to its iterative nature, there is ample opportunity to plug in computationally inexpensive fault tolerance schemes, many of which are also easy to implement. We experimentally examine the capability of various strategies to recover from single bit flips in time serial SDC, which will later be applied to parallel-in-time methods.
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