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@INPROCEEDINGS{Otten:916931,
      author       = {Otten, Rene and Schreckenberg, Lea and Vliex, Patrick and
                      Ritzmann, Julian and Ludwig, Arne and Wieck, Andreas D. and
                      Bluhm, Hendrik},
      title        = {{Q}ubit {B}ias using a {CMOS} {DAC} at m{K} {T}emperatures},
      school       = {RWTH Aachen University},
      reportid     = {FZJ-2023-00199},
      year         = {2022},
      abstract     = {Scaling up a quantum processor to tackle real-world
                      problems requires qubit numbers in the millions. Scalable
                      semiconductor-based architectures have been proposed, many
                      of them relying on integrated control instead of
                      room-temperature electronics. However, it has not yet been
                      shown that this can be achieved. For developing a
                      high-density, low-cost wiring solution, it is highly
                      advantageous for the electronics to be placed at the same
                      temperature as the qubit chip. Therefore, tight integration
                      of the qubit chip with ultra low power complementary
                      metal–oxide–semiconductor (CMOS) electronics presents a
                      promising route. We demonstrate DC biasing qubit electrodes
                      using a custom-designed 65nm CMOS capacitive
                      digital-to-analog converter (DAC) operating on the mixing
                      chamber of a dilution refrigerator below 45 mK. Our chip
                      features a complete proof of principle solution including
                      interface, DAC memory and logic, the capacitive DAC, and
                      sample-and-hold structures to provide voltages for multiple
                      qubit gates. The bias-DAC (CryoDAC) is combined with the
                      qubit using a silicon interposer chip, enabling flexible
                      routing and tight integration. Voltage stability, noise
                      performance, and temperature are benchmarked using the qubit
                      chip. Our results indicate that qubit bias at cryogenic
                      temperatures with a power consumption of 4 nW/ch is feasible
                      with this approach. They validate the potential of very low
                      power qubit biasing using highly integrated circuits whose
                      connectivity requirements do not increase with the number of
                      qubits.},
      month         = {Sep},
      date          = {2022-09-05},
      organization  = {5th International Conference on
                       Spin-Based Quantum Information
                       Processing (Spin Qubit 5), Pontresina
                       (Switzerland), 5 Sep 2022 - 9 Sep 2022},
      subtyp        = {After Call},
      cin          = {PGI-11 / ZEA-2},
      cid          = {I:(DE-Juel1)PGI-11-20170113 / I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {5221 - Advanced Solid-State Qubits and Qubit Systems
                      (POF4-522) / BMBF-13N16149 - QSolid (BMBF-13N16149)},
      pid          = {G:(DE-HGF)POF4-5221 / G:(DE-Juel1)BMBF-13N16149},
      typ          = {PUB:(DE-HGF)24},
      url          = {https://juser.fz-juelich.de/record/916931},
}