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| Hauptseite > Publikationsdatenbank > Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation |
| Contribution to a conference proceedings/Contribution to a book | FZJ-2024-01918 |
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2024
ACM New York, NY, USA
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Please use a persistent id in citations: doi:10.1145/3642921.3642956
Abstract: The paper introduces a modeling methodology aimed at thoroughlyexploring the design space of multi-die chip architecture tailoredfor High-Performance Computing (HPC). For accurate simulations,we leverage the capabilities of gem5’s Ruby for its robust CPUmodels and cache coherence protocols, providing a comprehensiverepresentation of die architecture. Die-to-die interfaces are modeledusing SystemC TLM, offering flexibility to integrate with othersimulators. This enables co-simulation with varying abstractionlevels, making it well-suited for the design analysis of multi-diechip architecture.We present, to the best of our knowledge, the first attempt tointegrate gem5’s Ruby memory system with SystemC TLM for themodeling of multi-die chip architecture. The benefits of this modelare demonstrated through the instantiation of a multi-die designusing modern Arm architectures with four compute dies and twomemory dies. The multi-die chip’s functionality is validated byexecuting STREAM Triad with Linux, followed by a comparativeperformance analysis against a monolithic design.
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