Conference Presentation (After Call)

FZJ-2025-01009

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Porting Lattice QCD benchmark to upcoming STX stencil/tensor accelerator

Schlepphorst, S. (Corresponding author)FZJ* ; Krieg, S.FZJ*

2024

Abstract: Developed under the European Processor Initiative (EPI) the STX stencil/tensor accelerator aims to achieve a 5-10x higher energy efficiency over general purpose compute units. The architecture consists of specialised MIMD compute units which are supported and controlled by RISC-V cores. We describe a co-design effort between hardware, software, and application development focused around porting a LQCD benchmark to this new architecture.

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Contributing Institute(s):

1. Jülich Supercomputing Center (JSC)

Research Program(s):

1. 5111 - Domain-Specific Simulation & Data Life Cycle Labs (SDLs) and Research Groups (POF4-511) (POF4-511)

Appears in the scientific report 2024

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