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| Book/Dissertation / PhD Thesis | FZJ-2025-02815 |
2025
Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag
Jülich
ISBN: 978-3-95806-826-1
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Please use a persistent id in citations: urn:nbn:de:0001-2507141005594.112471051241 doi:10.34734/FZJ-2025-02815
Abstract: With ever increasing digital processing capabilities, the analog-to-digital converter moves more and more in the focus of analog integrated circuit design becoming one of the most important building blocks. The progression to modern process technology nodes offers great potential, but comes in general along with an exponential growth in time effort for design, layout and verification. The overall cost for projects exceeds the capacities in research traditionally coping with smaller budgets than industry. Future developments therefore have to be accomplished in joint efforts, distributing different circuit blocks among research groups. But this also implicates that future electronics become more generic covering multiple areas of application. In this thesis, the concept of a software-configurable analog-to-digital converter is proposed. Its matrix-like structure consisting of many sub analog-to-digital converters is able to adjust the resolution and sample rate, but ultimately the power consumption, to fit a wide range of applications in research. A first version of a software-configurable analog-to-digital converter can be switched from a high-precision mode with 11 bit resolution to a low-power mode with 8 bit. It is the focus of this work and is manufactured in a silicon 28 nm bulk CMOS process technology node. Its high integration factor allows the implementation of powerful digital signal processing on-chip, while analog performance and conventional design methodologies largely stay valid as it is still a planar bulk silicon process. In a first step, a chip was designed and manufactured featuring a 6 bit successive approximation register analog-to-digital converter. It served as a pilot project marking the transition from a previously used 65 nm technology process to a more modern 28 nm node at the institute. The main focus here was to identify the potential and also the drawbacks of the technology as well as to gather experience in the design of successive approximation register analog-to-digital converters. The results of literature research, design decisions, consequences and finally the measurement results are presented in detail. Subsequently, a second chip has a first version of a software-configurable analog-to-digital converter at its core. For the two sub analog-to-digital converters it is mainly based on, the experience from the first chip helped to accelerate the design and enabled significant improvements. Apart from that, further improvements were integrated on an architectural level to increase power efficiency and increase the competitiveness of a generic solution. Simulation and measurement results are presented in detail. Finally, an error analysis is given investigating the non optimal behavior of the high-precision mode.
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