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| Hauptseite > Publikationsdatenbank > Co-Simulation for Automated Optimization of Integrated Cryogenic Qubit Electronics |
| Hauptseite > Publikationsdatenbank > Co-Simulation for Automated Optimization of Integrated Cryogenic Qubit Electronics |
| Contribution to a conference proceedings/Contribution to a book | FZJ-2025-03423 |
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2025
IEEE
ISBN: 979-8-3315-2395-4
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Please use a persistent id in citations: doi:10.1109/SMACD65553.2025.11092223
Abstract: One approach to scaling quantum computers requires large-scale integration of qubit control electronics at cryogenic temperatures close to the qubits to reduce the wiring bottleneck, signal latencies, and improve the modularity of the system. Finding optimized specifications by accurately simulating the qubit-electronics interface allows optimal budgeting of resources (heat dissipation, area) for scalable quantum computers. We propose a systematic and efficient design flow for the optimization of integrated electronic circuits using a co-simulation methodology that covers the entire development process from the concept phase to transistor-level design. As a use case, we choose the shuttling of spin qubits inside quantum dots. The automated workflow optimizes the hardware parameters of the circuit during the design phase of the integrated circuit. Based on the simulated performance of our low-power circuits, we argue that well-designed integrated electronics can replace critically-scaling room-temperature electronics for the given use case.
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