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| Journal Article | FZJ-2026-02724 |
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2026
IOP Publishing Ltd.
Bristol
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Please use a persistent id in citations: doi:10.1088/2634-4386/ae65d5 doi:10.34734/FZJ-2026-02724
Abstract: Logic-in-memory (LiM) has emerged as a promising paradigm to address the von Neumann bottleneck by integrating data storage and in-situ computation. Resistive random-access memory (RRAM) is a strong candidate for LiM owing to its non-volatility, fast switching characteristics, and compatibility with CMOS integration. However, intrinsic cycle-to-cycle and device-to-device variability fundamentally limits logic reliability in RRAM-based LiM architectures, necessitating well-defined device specifications and variability margins to ensure correct operation. In this work, we experimentally demonstrate a CMOS-integrated TaOx-based 1T1R RRAM computing fabric that supports reconfigurable LiM operations, including a functionally complete Boolean set and in-memory arithmetic primitives. Through extensive statistical measurements and variability-aware statistical modeling, we systematically evaluate the impact of key variability sources, SET voltage (VSET), low resistance state, and high resistance state, on logic correctness and identify the dominant contributors to computational failure. Finally, we derive the device specifications and requirements to achieve error-free stateful LiM operations in the 1T1R RRAM arrays.
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