Journal Article PreJuSER-12008

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n-Channel MOSFETs Fabricated on SiGe Dots for Strain-Enhanced Mobility

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2010
IEEE New York, NY

IEEE Electron Device Letters 31, 1083 - 1085 () [10.1109/LED.2010.2058995]

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Abstract: The silicon germanium dots grown in the Stranski-Krastanow mode are used to induce biaxial tensile strain in a silicon capping layer. A high Ge content and correspondingly high Si strain levels are reached due to the 3-D growth of the dots. The n-channel MOS devices, referred to in this letter as DotFETs, are processed with the main gate segment above the strained Si layer on a single dot. To prevent the intermixing of the Si/SiGe/Si structure, a novel low-temperature FET structure processed below 400 degrees C has been implemented: The ultrashallow source/drain junctions formed by excimer-laser annealing in the full-melt mode of ion-implanted dopants are self-aligned to a metal gate. The crystallinity of the structure is preserved throughout the processing, and compared to reference devices, an average increase in the drain current of up to 22.5% is obtained.

Keyword(s): J ; CMOS (auto) ; excimer-laser annealing (ELA) (auto) ; low-temperature gate stack (auto) ; SiGe (auto) ; strain-enhanced mobility (auto) ; Stranski-Krastanow (S-K) growth mode (auto) ; ultrashallow source/drain junctions (auto)


Note: This work was supported by the European Commission's Sixth Framework Programme under the D-Dot FET project. The review of this letter was arranged by Editor K. De Meyer.

Contributing Institute(s):
  1. Halbleiter-Nanoelektronik (IBN-1)
  2. Jülich-Aachen Research Alliance - Fundamentals of Future Information Technology (JARA-FIT)
Research Program(s):
  1. Grundlagen für zukünftige Informationstechnologien (P42)

Appears in the scientific report 2010
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 Record created 2012-11-13, last modified 2018-02-08



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