Lecture (After Call) FZJ-2019-06785

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Application Porting and Optimization on GPU-Accelerated POWER Architectures

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2019

Lecture at International Conference for High Performance Computing, Networking, Storage and Analysis (The Supercomputing Conference) (Denver, CO, USA), 18 Nov 2019 - 18 Nov 20192019-11-182019-11-18

Abstract: The POWER processor has re-emerged as a technology for supercomputer architectures. One major reason is the tight integration of processor and GPU accelerator through the NVLink technology. Two major sites in the US, ORNL and LLNL, deployed their pre-exascale systems based on this new architecture (Summit and Sierra, respectively).This tutorial gives an opportunity to obtain in-depth knowledge and experience with GPU-accelerated POWER nodes. It focuses on porting applications to a single node and covers the topics architecture, compilers, performance analysis and tuning, and multi-GPU programming. The tutorial includes an overview of the NVLink-based node architectures, lectures on first-hand experience in porting to this architecture, and exercises using tools to focus on performance.


Contributing Institute(s):
  1. Jülich Supercomputing Center (JSC)
Research Program(s):
  1. 511 - Computational Science and Mathematical Methods (POF3-511) (POF3-511)
  2. 513 - Supercomputer Facility (POF3-513) (POF3-513)

Appears in the scientific report 2019
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 Record created 2019-12-18, last modified 2021-01-30


Restricted:
1-Hardware_Architecture - Download fulltext PDF Download fulltext PDF (PDFA)
4-Volta_GPU_Architecture - Download fulltext PDF
6-Best_Practices - Download fulltext PDF Download fulltext PDF (PDFA)
2-Performance_Counters - Download fulltext PDF Download fulltext PDF (PDFA)
5-Multi_GPU_Programming - Download fulltext PDF
3-Compiler_Optimizations - Download fulltext PDF Download fulltext PDF (PDFA)
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