Conference Presentation (Panel discussion)

FZJ-2022-03604

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png GeSn Vertical Gate-all-around Nanowire n-type MOSFETs

Junk, Y. (Corresponding author)FZJ* ; Frauenrath, M. ; Han, Y.FZJ* ; Concepción Díaz, O.FZJ* ; Bae, J. H.FZJ* ; Hartmann, J.-M. ; Grützmacher, D.FZJ* ; Buca, D. M.FZJ* ; Zhao, Q.-T.FZJ*

2022

Abstract: Vertical GeSn gate-all-around (GAA) nanowire nMOSFETs fabricated using a top-down approach are presented. The devices are benchmarked with similar Ge and Ge/GeSn/Ge heterostructure devices to underline the great potential of GeSn for future nMOS devices. Device measurements are performed in the temperature range from 12 K to room temperature (RT, 300 K). At RT the all-GeSn n-MOSFETs show a subthreshold swing (SS) of ~120 mV/dec that decreases at cryogenic temperatures to a very steep 20mV/dec. The abrupt transition from subthreshold to on-state shows the suitability of GeSn alloys for cryogenic CMOS applications.

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Contributing Institute(s):

1. Halbleiter-Nanoelektronik (PGI-9)

Research Program(s):

1. 5234 - Emerging NC Architectures (POF4-523) (POF4-523)

Appears in the scientific report 2022

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