Journal Article

FZJ-2023-02380

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Vertical GeSn nanowire MOSFETs for CMOS beyond silicon

Liu, M.FZJ* ; Junk, Y.FZJ* ; Han, Y.FZJ* ; Yang, D.FZJ* ; Bae, J. H.FZJ* ; Frauenrath, M. ; Hartmann, J.-M. ; Ikonic, Z. ; Bärwolf, F. ; Mai, A. ; Grützmacher, D.FZJ* ; Knoch, J. ; Buca, D.FZJ* ; Zhao, Q.-T. (Corresponding author)FZJ*

2023
Nature Publishing Group UK [London]

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Please use a persistent id in citations: doi:10.1038/s44172-023-00059-2  doi:10.34734/FZJ-2023-02380

Abstract: The continued downscaling of silicon CMOS technology presents challenges for achieving the required low power consumption. While high mobility channel materials hold promise for improved device performance at low power levels, a material system which enables both high mobility n-FETs and p-FETs, that is compatible with Si technology and can be readily integrated into existing fabrication lines is required. Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transconductance is increased to 850 µS/µm by exploiting the small band gap of GeSn as source yielding high injection velocities, the mobility in n-FETs is increased 2.5-fold compared to a Ge reference device, by using GeSn as channel material. The potential of the material system for a future beyond Si CMOS logic and quantum computing applications is demonstrated via a GeSn inverter and steep switching at cryogenic temperatures, respectively.

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Contributing Institute(s):

1. Halbleiter-Nanoelektronik (PGI-9)
2. JARA-FIT (JARA-FIT)

Research Program(s):

1. 5234 - Emerging NC Architectures (POF4-523) (POF4-523)

Appears in the scientific report 2023

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