Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines

Hizzani, Mohammad; Van Vaerenbergh, Thomas; Hutchinson, George; Bhattacharya, Tinish; Strachan, John Paul; Heittmann, Arne; Dobrynin, Dmitri; Renaudineau, Adrien; Strukov, Dmitri

doi:10.48550/arXiv.2311.01171

Preprint

FZJ-2023-04417

Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines

Hizzani, M. (Corresponding author)FZJ* ; Heittmann, A.FZJ* ; Hutchinson, G. ; Dobrynin, D.FZJ* ; Van Vaerenbergh, T. ; Bhattacharya, T. ; Renaudineau, A.FZJ* ; Strukov, D. ; Strachan, J. P.FZJ*

2023
arXiv

arXiv (2023) [10.48550/arXiv.2311.01171]

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Please use a persistent id in citations: doi:10.48550/ARXIV.2311.01171 doi:10.48550/arXiv.2311.01171 doi:10.34734/FZJ-2023-04417

Report No.: 2311.01171

Abstract: Ising solvers offer a promising physics-based approach to tackle the challenging class of combinatorial optimization problems. However, typical solvers operate in a quadratic energy space, having only pair-wise coupling elements which already dominate area and energy. We show that such quadratization can cause severe problems: increased dimensionality, a rugged search landscape, and misalignment with the original objective function. Here, we design and quantify a higher-order Hopfield optimization solver, with 28nm CMOS technology and memristive couplings for lower area and energy computations. We combine algorithmic and circuit analysis to show quantitative advantages over quadratic Ising Machines (IM)s, yielding 48x and 72x reduction in time-to-solution (TTS) and energy-to-solution (ETS) respectively for Boolean satisfiability problems of 150 variables, with favorable scaling.

Keyword(s): Others (2nd) ; Emerging Technologies (cs.ET) ; Hardware Architecture (cs.AR) ; FOS: Computer and information sciences

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