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| Hauptseite > Publikationsdatenbank > Strained Silicon and Silicon-Germanium Nanowire Tunnel FETs and Inverters |
| Hauptseite > Publikationsdatenbank > Strained Silicon and Silicon-Germanium Nanowire Tunnel FETs and Inverters |
| Book/Dissertation / PhD Thesis | FZJ-2015-00861 |
2014
Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag
Jülich
ISBN: 978-3-95806-002-9
Please use a persistent id in citations: http://hdl.handle.net/2128/8459
Abstract: Reducing power consumption is an important issue for integrated circuits in portable devices relying on batteries and systems without external power supply. Scaling of the supply voltage V$_{DD}$ in integrated circuits is a powerful tool for reducing the power consumption, due to the quadratic dependence on V$_{DD}$. MOSFETs, however, exhibit a fundamental limitation forthe drain current increase per applied gate voltage difference. The tunnel field-effect transistor(TFET) provides the ability for beating this limitation, thus offering a performanceadvantage over MOSFETs for ultra-low V$_{DD}$. In this work, TFETs are fabricated with respect to design rules deduced from basic physical relations for the tunneling probability. The aim is to increase the tunneling probability in order to obtain higher drive currents in the devices. A tri-gated nanowire design in combinationwith a high-$\ κappa$/metal gate stacks is employed in order to increase the electrostatic gate control. Devices are fabricated on tensile-strained Si on insulator (SSOI) as well as compressively strained SiGe on SOI substrates. Fabricated devices reveal enhanced current for smaller band gap and effective carrier mass in those materials. In order to further increase I$_{ON}$ and prevent I$_{OFF}$ degradation occurring in small band gap TFET homostructures, a NW based heterostructure design with enlarged tunnel junction area is conceived and fabricated. Device characterization of this structure reveals superior performance and large I$_{ON}$/I$_{OFF}$ ratio. TCAD simulations demonstrate how the structure could be adapted toutilize line tunneling in an inverted source region for further current improvement. SSOI NW TFET characteristics are investigated and compared to MOSFETs fabricated with analog processing. Temperature dependence of TFET characteristics is analyzed and hot carrier effects in the tunnel junction are revealed by charge pumping measurements. Furthermore, the feasibility of TFETs for logic application is studied by fabrication of inverter structures. A comparison of TFET and MOSFET inverters reveals degradation of the voltage transfer characteristics caused by the ambipolarity of TFETs. An emulated TFET structure based on the fabricated SiGe/Si heterostructure with reduced ambipolarity provesto prevent output degradation of the TFET inverter and demonstrates sufficiently high noisemargins down to ultra-low supply voltages. Low frequency noise measurements are performed on SSOI NW TFETs and MOSFETs revealinga dominant noise contribution by the tunnel junction in TFETs. The confined tunnel junction area provides a higher probability for RTS noise generation.
Keyword(s): Dissertation
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