Home > Publications database > Examination of a new SiGe/Si heterostructure TFET concept based on vertical tunneling |
Contribution to a conference proceedings/Contribution to a book | FZJ-2019-00019 |
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2017
IEEE
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Please use a persistent id in citations: doi:10.1109/E3S.2017.8246169
Abstract: This paper presents a Tunneling Field Effect Transistor concept with a vertical SiGe/Si hetero tunneling junction utilizing a design which promotes line tunneling in a source-gate overlap region. By contrast, the influence of parasitic point tunneling is marginal in the structure, resulting in a sharp turn-on. We show that the growth of a suitable layer stack and manufacturing a device is perfectly feasible and provide first electrical measurements serving as a proof of concept. The route to enhancing the performance by scaling device dimensions and adjusting the channel doping is examined by means of TCAD simulations.
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