Contribution to a conference proceedings/Journal Article

FZJ-2013-03232

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png SEU tolerant memory design for the ATLAS pixel readout chip

Menouni, M. (Corresponding author) ; Arutinov, D. ; Backhaus, M.FZJ* ; Barbero, M. ; Beccherle, R. ; Breugnon, P. ; Caminada, L. ; Dube, S. ; Darbo, G. ; Fleury, J. ; Fougeron, D. ; Garcia-Sciveres, M. ; Gensolen, F. ; Gnani, D. ; Gonella, L. ; Gromov, V. ; Hemperek, T. ; Jensen, F. ; Karagounis, M. ; Kluit, R. ; Krueger, H. ; Kruth, A.ZEA-2* ; Lu, Y. ; Rozanov, A. ; Schipper, J. -. ; Zivkovic, V. ; Mekkaoui, A.

2013
Inst. of Physics London

This record in other databases:    

Please use a persistent id in citations: doi:10.1088/1748-0221/8/02/C02026

Abstract: The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

---

Contributing Institute(s):

1. Zentralinstitut für Elektronik (ZEA-2)

Research Program(s):

1. 899 - ohne Topic (POF2-899) (POF2-899)

Appears in the scientific report 2013

---

Database coverage:
; Current Contents - Social and Behavioral Sciences ; JCR ; Nationallizenz ; SCOPUS ; Science Citation Index Expanded ; Thomson Reuters Master Journal List ; Web of Science Core Collection

---