Contribution to a conference proceedings/Contribution to a book

FZJ-2019-00013

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Realization of vertical Ge nanowires for gate-all-around transistors

Liu, M. (Corresponding author)FZJ* ; Mertens, K.FZJ* ; Glass, S.FZJ* ; Mantl, S.FZJ* ; Buca, D.FZJ* ; Zhao, Q. T.FZJ* ; Trellenkamp, S.FZJ*

2018
IEEE Piscataway, NJ
ISBN: 978-1-5386-4811-7, 9781538648100, 9781538648124 (print)

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Please use a persistent id in citations: doi:10.1109/ULIS.2018.8354771

Abstract: Towards gate-all-around (GAA) FETs, we present the top-down realization of vertical Ge nanowires (NWs) with defect-free sidewall and perfect anisotropy. The NW patterns are transferred by a novel inductively coupled plasma reactive ion etching (ICP-RIE) technique. With optimized etching conditions, sub-60 nm diameter Ge nanowires are guaranteed while mitigating micro-trenching and under-cutting effects. To further shrink the NW diameter, digital etching is followed including multiple cycles of self-limited O2 plasma oxidation and diluted HF rinsing. O2 plasma is also utilized for surface passivation in Ge MOScaps to improve the high-k/Ge interface. These NWs form the base of vertical transistors which are simulated by TCAD tools here. The processing techniques proposed in this work provide a viable option for low power vertical Ge and GeSn NW transistors.

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Contributing Institute(s):

1. Halbleiter-Nanoelektronik (PGI-9)

Research Program(s):

1. 521 - Controlling Electron Charge-Based Phenomena (POF3-521) (POF3-521)

Appears in the scientific report 2018

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