Contribution to a conference proceedings/Contribution to a book

FZJ-2025-05555

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Porting Lattice QCD benchmark to upcoming STX stencil/tensor accelerator

Schlepphorst, S. (Corresponding author)FZJ* ; Krieg, S.FZJ*

2025
Sissa Medialab Trieste, Italy Trieste, Italy

This record in other databases:  

Please use a persistent id in citations: doi:10.22323/1.466.0451

Abstract: Developed under the European Processor Initiative (EPI), the STX stencil/tensor accelerator aims to achieve a 5-10x higher energy efficiency over general purpose compute units. The architecture consists of specialized MIMD compute units which are supported and controlled by RISC-V cores. We describe a co-design effort between hardware, software, and application development focused around porting a LQCD benchmark to this new architecture.

---

Contributing Institute(s):

1. Jülich Supercomputing Center (JSC)

Research Program(s):

1. 5111 - Domain-Specific Simulation & Data Life Cycle Labs (SDLs) and Research Groups (POF4-511) (POF4-511)
2. DFG project G:(GEPRIS)460248186 - PUNCH4NFDI - Teilchen, Universum, Kerne und Hadronen für die NFDI (460248186) (460248186)
3. EPI SGA2 (16ME0507K) (16ME0507K)
4. STXDemo - Energieoptimierte Supercomputer-Hardware durch Stencil- und Tensor-Beschleuniger (BMFTR-16ME0605) (BMFTR-16ME0605)

Appears in the scientific report 2025

---