Contribution to a conference proceedings FZJ-2019-00038

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Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs

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2017
IEEE

2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), AthensAthens, Greece, 3 Apr 2017 - 5 Apr 20172017-04-032017-04-05 IEEE 1-4 () [10.1109/ULIS.2017.7962584]

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Abstract: In this paper a compact model for intrinsic capacitances for Tunnel field-effect transistors (TFETs) is presented. The model is derived from the carrier concentration and current flowing the channel of a Si Double-Gate (DG) n-type TFET. It represents a particularly good estimation of TFET capacitances and the flexibility of this model makes it possible to apply it for single-gate or p-type TFETs as well. To verify the model, the results are compared with TCAD Sentaurus simulations as well as measurement data. In both case model shows satisfying results.


Contributing Institute(s):
  1. Halbleiter-Nanoelektronik (PGI-9)
Research Program(s):
  1. 521 - Controlling Electron Charge-Based Phenomena (POF3-521) (POF3-521)

Appears in the scientific report 2018
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 Record created 2019-01-03, last modified 2021-01-30


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