Gast ::
| Hauptseite > Publikationsdatenbank > Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm |
| Hauptseite > Publikationsdatenbank > Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm |
| Journal Article | FZJ-2020-01582 |
; ; ; ; ; ; ; ;
2020
IEEE
New York, NY
This record in other databases: 
Please use a persistent id in citations: http://hdl.handle.net/2128/25175 doi:10.1109/LED.2020.2971034
Abstract: In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl 2 -based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.
; Clarivate Analytics Master Journal List ; Current Contents - Engineering, Computing and Technology ; IF < 5 ; JCR ; SCOPUS ; Science Citation Index ; Science Citation Index Expanded ; Web of Science Core Collection
|
The record appears in these collections: |
PDF
PDF (PDFA)