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| Home > Publications database > Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations |
| Journal Article | FZJ-2018-02292 |
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2018
IEEE
[New York, NY]
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Please use a persistent id in citations: http://hdl.handle.net/2128/19674 doi:10.1109/JEDS.2018.2825639
Abstract: A half SRAM cell with strained Si nanowire complementary Tunnel-FETs (CTFET) was fabricated and characterized to explore the feasibility and functionality of 6T-SRAM based on TFETs. Outward-faced n-TFETs are used as access-transistors. Static measurements were performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage of the access-transistor at certain bias configurations leads to malfunctioning storage operation, even without the contribution of the ambipolar behavior. At large VDD, lowering of the bit-line bias is needed to mitigate such effect, demonstrating functional hold, read and write operations. Circuit simulations were carried out using a Verilog-A compact model calibrated on the experimental TFETs, providing a better understanding of the TFET SRAM operation at different supply voltages and for different cell sizing and giving an estimate of the dynamic performance of the cell.
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